Introduction
●The Intel® 82541(PI/GI/EI) Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel® 82541(PI/GI/EI) allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs.
●Product Features
●■ PCI Bus
●— PCI revision 2.3, 32-bit, 33/66 MHz
●— Algorithms that optimally use advanced PCI MWI, MRM, and MRL commands
●— CLK_RUN# signal
●— 3.3 V (5 V tolerant PCI signaling)
●■ MAC Specific
●— Low-latency transmit and receive queues
●— IEEE 802.3x-compliant flow-control support with software-controllable thresholds
●— Caches up to 64 packet descriptors in a single burst
●— Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B)
●— Wide, optimized internal data path architecture
●— 64 KB configurable Transmit and Receive FIFO buffers
●■ PHY Specific
●— Integrated for 10/100/1000 Mb/s full- and half-duplex operation
●— IEEE 802.3ab Auto-Negotiation and PHY compliance and compatibility
●— State-of-the-art DSP architecture implements digital adaptive equalization, echo and cross talk cancellation
●— Automatic polarity detection
●— Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds
●■ Host Off-Loading
●— Transmit and receive IP, TCP, and UDP checksum off-loading capabilities
●— Transmit TCP segmentation and advanced packed filtering
●— IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for up to 4096 VLAN tags
●— Jumbo frame support up to 16 KB
●— Intelligent Interrupt generation (multiple packets per interrupt)
●■ Manageability
●— On-chip SMBus 2.0 port
●— ASF 1.0 and 2.0
●— Compliance with PCI Power Management v1.1/ACPI v2.0
●— Wake on LAN
● (WoL) support
●— Smart Power Down mode when no signal is detected on the wire
●— Power Save mode switches link speed from 1000 Mb/s down to 10 or 100 Mb/s when on battery power
●■ Additional Device
●— Four programmable LED outputs
●— On-chip power regulator control circuitry
●— BIOS LAN Disable pin
●— JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V, 5 V tolerant PCI signaling)
