| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 80 Pin |
| Supply Voltage (DC) | 2.20V (min) |
| Case/Package | LQFP-80 |
| Output Voltage | 1.25 V |
| Supply Current | 180 mA |
| Number of Channels | 3 Channel |
| Number of Positions | 80 Position |
| Power Dissipation | 525 mW |
| Bandwidth | 300 MHz |
| Number of ADCs | 3 ADC |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Power Dissipation (Max) | 650 mW |
| Number of Input Channels | 3 Channel |
| Supply Voltage | 3V ~ 3.6V |
| Supply Voltage (Max) | 3.6 V |
| Supply Voltage (Min) | 2.2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tray |
| Size-Length | 14 mm |
| Size-Width | 14 mm |
| Size-Height | 1.45 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The AD9883AKSTZ-110 is a monolithic Analogue Interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140MSPS encode rate capability and full power analogue bandwidth of 300MHz supports resolutions up to SXGA (1280 x 1024 at 75Hz). It includes a 140MHz triple ADC with internal 1.25V reference, a PLL and programmable gain, offset and clamp control. The user provides only a 3.3V power supply, analogue input and Hsync and COAST signals. Three-state CMOS outputs may be powered from 2.5 to 3.3V. The AD9883A"s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 to 140MHz. PLL clock jitter is 500ps p-p typical at 140MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync and clock output phase relationships are maintained.
● Industrial temperature range operation
● Full sync processing
● Sync detect for hot plugging
● Midscale clamping
● Power-down mode
● 140MSPS Maximum conversion rate
● 300MHz Analogue bandwidth
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