| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | DIP-16 |
| Number of Outputs | 1 Output |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Clock Speed | 4.8 MHz |
| Number of Bits | 1 Bit |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Output Current Drive | -3.20 mA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Operating Temperature | -55℃ ~ 125℃ |
The CD40103BE is a 8-stage 8-bit presettable CMOS Binary Synchronous Down Counter with a single output which is active when the internal count is zero. It has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the carry-out/zero-defect output is active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the carry-in/counter enable (CI/CE\\) input is high. The carry-out/zero-defect (CO/ZD\\) output goes low when the count reaches zero if the CI/CE\ input is low and remains low for one full clock period. When the synchronous preset-enable (SPE\\) input is low, data at the JAM input is clocked input the counter on the next positive clock transition regardless of the state of the CI/CE\ input.
● Synchronous or asynchronous preset
● Cascadable
● 100% Tested for quiescent current at 20V
● Standardized symmetrical output characteristics
Intersil
Obsolete Product Datasheet
TI
TEXAS INSTRUMENTS CD40103BE Binary Synchronous Down Counter, 4.8MHz, 3V to 18V, DIP-16
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Counter Single 8Bit Sync/Async Binary Down 16Pin SOP T/R
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