| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 17 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 15.0 V, 18.0 V (max) |
| Operating Voltage | 3V ~ 18V |
| Case/Package | DIP-16 |
| Number of Outputs | 4 Output |
| Supply Current | 600 μA |
| Number of Circuits | 2 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 4 Bit |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Input Capacitance | 5 pF |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Width | 6.35 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4015BE is a 4-stage CMOS dual static Shift Register consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent clock and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the RESET line.
● Fully static operation
● Standardized, symmetrical output characteristics
● Meets all requirements of JEDEC tentative standard no. 13B
● 8 Master-slave flip-flops plus input and output buffering
● 100% Tested for quiescent current at 20V
● Green product and no Sb/Br
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