| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | SOIC-16 |
| Number of Outputs | 1 Output |
| Output Current | 6.8 mA |
| Number of Circuits | 4 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 300 ns |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Number of Gates | 4 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 9.9 mm |
| Size-Width | 3.91 mm |
| Size-Height | 1.58 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4019BM is a CMOS quad AND/OR select Gate consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
● 60ns Medium speed operation
● Standardized symmetrical output characteristics
● 100% Tested for quiescent current at 20V
● Meets all requirements of JEDEC tentative standard No. 13B
● 1µA at 18V Maximum input current
● 2.5V at VDD = 15V Noise margin
● Green product and no Sb/Br
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