TYPE | DESCRIPTION |
---|
Mounting Style | Surface Mount |
Frequency | 24 MHz |
Number of Pins | 16 Pin |
Supply Voltage (DC) | 3.00V (min) |
Case/Package | TSSOP-16 |
Number of Outputs | 1 Output |
Output Current | 6.8 mA |
Number of Circuits | 2 Circuit |
Number of Channels | 2 Channel |
Number of Positions | 16 Position |
Clock Speed | 24 MHz |
Number of Bits | 2 Bit |
Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
Input Capacitance | 5 pF |
Number of Inputs | 2 Input |
Operating Temperature (Max) | 125 ℃ |
Operating Temperature (Min) | -55 ℃ |
Supply Voltage | 3V ~ 18V |
Supply Voltage (Max) | 18 V |
Supply Voltage (Min) | 3 V |
TYPE | DESCRIPTION |
---|
Product Lifecycle Status | Active |
Packaging | Tube |
Size-Length | 5.1 mm |
Size-Width | 4.5 mm |
Size-Height | 1.05 mm |
Operating Temperature | -55℃ ~ 125℃ (TA) |
The CD4027BPW is a CMOS dual J-K Master-slave Flip-flop useful in performing control, register and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop, changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input. Each flip-flop has provisions for individual J, K, set, reset and Clock input signals. Buffered Q and Q\ signals are provided as outputs. This input-output arrangement provides for compatible operation with the RCA-CD4013B dual D-type flip-flop.
● Set-reset capability
● Static flip-flop operation
● Standardized symmetrical output characteristics
● 100% Tested for quiescent current at 20V
● Green product and no Sb/Br
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