| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 15.0 V, 18.0 V (max) |
| Case/Package | PDIP-16 |
| Number of Outputs | 4 Output |
| Output Current | 6.8 mA |
| Number of Circuits | 4 Circuit |
| Number of Channels | 4 Channel |
| Number of Positions | 16 Position |
| Number of Bits | 4 Bit |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Quiescent Current | 40.0 nA |
| Input Capacitance | 5.00 pF |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4042BE is a CMOS Quad-clocked "D" Latch, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n and p-channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY=0 the transfer occurs during the 0 CLOCK level and for POLARITY=1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY=0 and negative for POLARITY=1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
● Clock polarity control
● Q and Q\ outputs
● Common clock
● Low power TTL compatible
● Standardized, symmetrical output characteristics
● 100% Tested for quiescent current at 20V
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TEXAS INSTRUMENTS CD4042BEE4 Latch, CD4042, D Type, Differential, 40ns, 6.8mA, DIP
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