| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 15.0 V, 18.0 V (max) |
| Case/Package | PDIP-16 |
| Number of Outputs | 4 Output |
| Output Current | 6.8 mA |
| Number of Circuits | 1 Circuit |
| Number of Channels | 4 Channel |
| Number of Positions | 16 Position |
| Number of Bits | 4 Bit |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Quiescent Current | 40.0 nA |
| Input Capacitance | 5.00 pF |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4044BE is a quad CMOS NAND SR Latch with 3-state outputs. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic 1 or high on the ENABLE input connects the latch states to the Q outputs. A logic 0 or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
● Standardized symmetrical output characteristics
● 100% Tested for quiescent current at 20V
● Holding register in multi-register system
● Four bits of independent storage with OE
● Strobed register
● Negative logic systems
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