| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | SOP-14 |
| Number of Outputs | 1 Output |
| Output Current | 6.80 mA |
| Number of Circuits | 2 Circuit |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 250 ns |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Quiescent Current | 20.0 nA |
| Number of Gates | 2 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 10.3 mm |
| Size-Width | 5.3 mm |
| Size-Height | 1.95 mm |
| Operating Temperature | -55℃ ~ 125℃ |
CMOS OR Gates
●OR gates provide the system designer with direct implementation of the positive-logic OR
●function and supplement the existing family of CMOS gates.
●The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line
●ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
TI
OR Gate 2Element 4IN CMOS 14Pin PDIP Tube
TI
OR Gate 2Element 4IN CMOS 14Pin SOIC T/R
TI
OR Gate 2Element 4IN CMOS 14Pin SOIC Tube
TI
TEXAS INSTRUMENTS CD4072BPW OR Gate, CD4072 Series, High Voltage, 4Input, 6.8mA, 3V to 18V, TSSOP-14
TI
OR Gate 2Element 4IN CMOS 14Pin SOP T/R
TI
OR Gate 2Element 4IN CMOS 14Pin SOIC T/R
TI
OR Gate 2Element 4IN CMOS 14Pin CDIP Tube
TI
OR Gate 2Element 4IN CMOS 14Pin SOIC T/R
TI
OR Gate 2Element 4IN CMOS 14Pin SOIC Tube
TI
OR Gate 2Element 4IN CMOS 14Pin PDIP Tube
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.
