| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | CDIP |
| Number of Outputs | 1 Output |
| Number of Bits | 3 Bit |
| Propagation Delay Max (tpd) | 250 ns |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Number of Gates | 3 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 3 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Operating Temperature | -55℃ ~ 125℃ |
CMOS OR Gates
●OR gates provide the system designer with direct implementation of the positive-logic OR
●function and supplement the existing family of CMOS gates.
●The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line
●ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
TI
OR Gate 3Element 3IN CMOS 14Pin PDIP Tube
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OR Gate 3Element 3IN CMOS 14Pin SOIC T/R
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OR Gate 3Element 3IN CMOS 14Pin SOIC Tube
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OR Gate 3Element 3IN CMOS 14Pin TSSOP T/R
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OR Gate 3Element 3IN CMOS 14Pin TSSOP Tube
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OR Gate 3Element 3IN CMOS 14Pin SOP T/R
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OR Gate 3Element 3IN CMOS 14Pin CDIP Tube
TI
OR Gate 3Element 3IN CMOS 14Pin PDIP Tube
TI
OR Gate 3Element 3IN CMOS 14Pin CDIP Tube
TI
OR Gate 3Element 3IN CMOS 14Pin TSSOP T/R
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