| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | PDIP-16 |
| Number of Outputs | 4 Output |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 8 MHz |
| Number of Bits | 4 Bit |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Number of Gates | 2 Gate |
| Input Capacitance | 5.00 pF |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4520BE is a CMOS dual binary Up-counter consists of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counter is cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.
● Positive- or negative-edge triggering
● Synchronous internal carry propagation
● 100% Tested for quiescent current at 20V
● Standardized, symmetrical output characteristics
● Meets all requirements of JEDEC tentative standard #13B
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