| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 100 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | SOIC-16 |
| Number of Outputs | 1 Output |
| Output Current | 24 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 100 MHz |
| Number of Bits | 2 Bit |
| Polarity | Non-Inverting, Inverting |
| Input Capacitance | 10 pF |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 1.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 1.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 9.9 mm |
| Size-Width | 3.91 mm |
| Size-Height | 1.5 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74AC112M is a dual negative-edge-triggered J-K Flip-flop with set and reset. It contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip-flop can perform as toggle flip-flop by tying J and K high.
● Speed of Bipolar F, AS and S, with significantly reduced power consumption
● Balanced propagation delays
● ±24mA Output drive current
● SCR-Latchup-resistant CMOS process and circuit design
● Green product and no Sb/Br
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