The CD74HC107E is a high speed CMOS dual negative-edge-triggered J-K Flip-flop with reset. It utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent J, K, Reset and Clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.
● Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
● Asynchronous reset
● Complementary outputs
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
● High noise immunity
● Direct LSTTL input logic compatibility
● CMOS Input compatibility
● 10 LSTTL Load standard outputs
● 15 LSTTL Load bus driver outputs
