| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.00V (min) |
| Case/Package | PDIP-16 |
| Number of Outputs | 4 Output |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Clock Speed | 24 MHz |
| Number of Bits | 4 Bit |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HC192E is a 4-bit high-speed CMOS logic presettable synchronous Up/Down Counter. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a low asynchronous parallel load input (PL). The counter is incremented on the low-to-high transition of the clock-up input (and a high level on the clock-down input) and decremented on the low to high transition of the clock-down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The terminal count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The terminal count down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count.
● Synchronous counting and asynchronous loading
● Two outputs for N-bit cascading
● Look-ahead carry for high-speed counting
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
● ±20mA DC input/output diode current
● 150°C Junction temperature
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