| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 55 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | PDIP-16 |
| Number of Outputs | 1 Output |
| Supply Current | 8.00 µA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 1 Bit |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Duty Cycle | 50 % |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HC297E is a high-speed silicon gate CMOS Device that is pin-compatible with low power Schottky TTL (LSTTL). This device is designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops. Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. The length of the up/down K-counter is digitally programmable according to the K-counter function table.
● Digital design avoids analog compensation errors
● Easily cascadable for higher order loops
● Dynamically variable bandwidth
● Very narrow bandwidth attainable
● Power-on reset
● Balanced Propagation Delay and Transition Times
● Significant Power Reduction Compared to LSTTL Logic ICs
TI
the hc297 and cd74hct297 are high-speed silicon gate cmos devices that are pin-compatible with low power schottky ttl...
TI
PLL, 55MHz, 4.5V to 5.5V, DIP-16
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.
