| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 20 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 5.00 V, 6.00 V (max) |
| Case/Package | DIP-20 |
| Number of Outputs | 8 Output |
| Output Current | 7.8 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Polarity | Non-Inverting |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HC373E is an octal CMOS Transparent Latch with 3-state outputs. This high speed latch is designed for 2 to 6V VCC operation. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.
● Balanced propagation delays and transition times
● Standard outputs drive up to 15 LS-TTL loads
● Significant power reduction compared to LS-TTL logic ICs
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TEXAS INSTRUMENTS CD74HC373EE4 Latch, HC Family, 74HC373, Transparent, Tri State, 26ns, 7.8mA, DIP
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