| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 5.00 V, 6.00 V (max) |
| Case/Package | PDIP-16 |
| Number of Outputs | 4 Output |
| Output Current | 5.2 mA |
| Number of Circuits | 2 Circuit |
| Number of Bits | 4 Bit |
| Polarity | Non-Inverting, Inverting |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Weight | 0.015227096868 kg |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HC75E is a 2-bit CMOS dual bistable Transparent Latch controlled by separate enable inputs (1E\ and 2E\\) which are active low. When the enable input is high data enters the latch and appears at the Q output. When the enable input (1E\ and 2E\\) is low the output is not affected.
● True and complementary outputs
● Buffered inputs and outputs
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
● High noise immunity
● Direct LSTTL input logic compatibility
● CMOS Input compatibility
TI
High Speed CMOS Logic Dual 2Bit Bistable Transparent Latches
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TEXAS INSTRUMENTS CD74HC75E Latch, HC Family, 74HC75, Bistable, Transparent, Differential, 9ns, 5.2mA, DIP
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Latch Transparent 4CH D-Type 16Pin SOIC Tube
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Latch Transparent 4CH D-Type 16Pin TSSOP Tube
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Latch Transparent 4CH D-Type 16Pin SOIC T/R
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Latch Transparent 4CH D-Type 16Pin SOIC T/R
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Latch Transparent 4CH D-Type 16Pin TSSOP T/R
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Latch Transparent 4CH D-Type 16Pin TSSOP T/R
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IC DUAL 2Bit TRANS LATCH 16SO
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Latch Transparent 4CH D-Type 16Pin PDIP Tube
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