The CDCM1802RGTT is a Clock Driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0 and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50R transmission lines. The LVCMOS output is delayed by 1.6ns over the PECL output stage to minimize noise impact during signal transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. It is characterized for operation from -40 to 85°C. For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.
● Distributes one differential clock input to one LVPECL output and one LVCMOS single-ended output
● Programmable output divider for both LVPECL and LVCMOS outputs
● Differential input stage for wide common-mode range
● 1.6ns Output skew between LVCMOS and LVPECL transitions minimizing noise
● ±75mV Receiver input threshold
●Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
