The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.
● Integrated Low-Noise Clock Generator Including
●PLL, VCO, and Loop Filter
● Two Low-Noise 100-MHz Clocks (LVPECL,
●LVDS, or pair of LVCMOS)
● Support for HCSL Signaling Levels
●(AC-Coupled)
● Typical Period Jitter: 21 ps pk-pk
● Typical Random Jitter: 510 fs RMS
● Output Type Set by Pins
● Bonus Single-Ended 25-MHz Output
● Integrated Crystal Oscillator Input Accepts
●25-MHz Crystal
● Output Enable Pin Shuts Off Device and Outputs
● 5-mm × 5-mm 32-Pin VQFN Package
● ESD Protection Exceeds 2000 V HBM, 500 V
●CDM
● Industrial Temperature Range (40°C to 85°C)
● 3.3-V Power Supply
