| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 8 Pin |
| Supply Voltage (DC) | 5.50V (max) |
| Case/Package | LSSOP-8 |
| Number of Outputs | 2 Output |
| Number of Channels | 2 Channel |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 3.70 ns |
| Voltage Nodes | 5.00 V, 3.30 V, 2.50 V, 1.80 V |
| Number of Gates | 2 Gate |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.65V ~ 5.5V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Operating Temperature | -40℃ ~ 85℃ (TA) |
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
●To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
●This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
TI
Buffer/Line Driver 2CH Non-Inverting 3-ST CMOS 8Pin SSOP T/R
TI
Buffer/Line Driver 2CH Non-Inverting 3-ST CMOS 8Pin VSSOP T/R
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