| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 133.33 MHz |
| Number of Pins | 8 Pin |
| Case/Package | SOIC-8 |
| Number of Outputs | 5 Output |
| Supply Current | 35 mA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 8 Position |
| Number of Inputs | 1 Input |
| Maximum Duty Cycle | 60 % |
| Fall Time (Max) | 2.25 ns |
| Fall Time (Max) | 2.25 ns |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 3V ~ 3.6V |
| Supply Voltage (Max) | 3.6 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 4.98 mm |
| Size-Width | 3.99 mm |
| Size-Height | 1.48 mm |
| Operating Temperature | -40℃ ~ 85℃ |
Functional Description
●The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309. The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.
●Features
●■10 MHz to 100–133 MHz operating range
●■Zero input and output propagation delay
●■Multiple low skew outputs
●■One input drives five outputs (CY2305C)
●■One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
●■50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
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LOW-COST 3.3V ZERO DELAY BUFFER
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