| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 28 Pin |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Operating Voltage | 5 V |
| Case/Package | DIP-28 |
| Supply Current | 50 mA |
| Number of Positions | 28 Position |
| Clock Speed | 70.0 GHz |
| Number of Bits | 8 Bit |
| Access Time | 70 ns |
| Memory Size | 32000 B |
| Access Time(Max) | 70 ns |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 37.59 mm |
| Size-Width | 13.97 mm |
| Size-Height | 9.14 mm |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
The CY62256NLL-70PXC is a high performance CMOS Static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remain inactive or HIGH.
● 55ns High speed
● 275mW Maximum low active power
● 82.5µW Maximum low standby power (LL version)
● TTL-compatible inputs and outputs
● CMOS for optimum speed and power
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