The DP83816 device is a single-chip 10/100 Mb/s ethernet controller for the PCI bus. It is targeted at low-cost, high-volume PC motherboards, adapter cards, and embedded systems. The DP83816 device fully implements the V2.2 33-MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 device can support full-duplex 10/100 Mb/s transmission and reception with minimum interframe gap.
● IEEE 802.3 Compliant, PCI V2.2 Media Access
●Controller (MAC) and Bus Interface Unit (BIU)
●Supports Traditional Data Rates of 10 Mb/s
●Ethernet and 100 Mb/s Fast Ethernet (Through
●Internal PHY)
● Bus Master – Burst Sizes of up to 128 Dwords
●(512 Bytes)
● BIU Compliant With PC 97 and PC 98 Hardware
●Design Guides, PC 99 Hardware Design Guide
●Draft, ACPI v1.0, PCI Power Management
●Specification v1.1, OnNow Device Class Power
●Management Reference Specification – Network
●Device Class v1.0a
● Wake on LAN (WoL) Support Compliant With
●PC98, PC99, SecureOn, and OnNow, Including
●Directed Packets, Magic Packet™ VLAN Packets,
●ARP Packets, Pattern Match Packets, and PHY
●Status Change
● Clkrun Function for PCI Mobile Design Guide
● Virtual LAN (VLAN) and Long Frame Support
● Support for IEEE 802.3× Full-Duplex Flow Control
● Extremely Flexible Rx Packet Filtration Including:
●Single Address Perfect Filter With MSb Masking,
●Broadcast, 512 Entry Multicast and Unicast Hash
●Table, Deep Packet Pattern Matching for up to
●Four Unique Patterns
● Statistics Gathered for Support of RFC 1213
●(MIB II), RFC 1398 (Ether-Like MIB), IEEE 802.3
●LME, Reducing CPU Overhead for Management
● Internal 2KB Transmit and 2KB Receive Data
●FIFOs
● Serial EEPROM Port With Auto-Load of
●Configuration Data From EEPROM at Power On
● Flash or PROM Interface for Remote Boot Support
● Fully Integrated IEEE 802.3 3.3-V CMOS Physical
●Layer
● IEEE 802.3 10BASE-T Transceiver With Integrated
●Filters IEEE 802.3u 100BASE-TX Transceiver
● Fully integrated ANSI X3.263 Compliant TP-PMD
●Physical Sublayer With Adaptive Equalization and
●Baseline Wander Compensation
● IEEE 802.3u Auto-Negotiation – Advertised
●Features Configurable Through EEPROM
● Full-Duplex Support for 10- and 100-Mb/s Data
●Rates
● Single 25-MHz Reference Clock
● 144-pin LQFP Package
● Low-Power 3.3-V CMOS Design With Typical
●Consumption of 383 mW Operating, 297 mW
●During WoL, and 53 mW During Sleep Mode
● IEEE 802.3u MII for Connecting Alternative
●External Physical Layer Devices
● 3.3-V Signaling With 5-V Tolerant I/O
