General Description
●The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices.
●Features
●■ Complies with OpenLDI specification for digital display interfaces
●■ 32.5 to 112/170MHz clock support for DS90C387, 40 to 112MHz clock support for DS90CF388
●■ Supports SVGA through QXGA panel resolutions
●■ Drives long, low cost cables
●■ Up to 5.38Gbps bandwidth
●■ Pre-emphasis reduces cable loading effects
●■ DC Balance data transmission provided by transmitter reduces ISI distortion
●■ Cable Deskew of +/−1 LVDS data bit time (up to 80 MHz Clock Rate) of pair-to-pair skew at receiver inputs; intra-pair skew tolerance of 300ps
●■ Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface
●■ Transmitter rejects cycle-to-cycle jitter
●■ 5V tolerant on data and control input pins
●■ Programmable transmitter data and control strobe select (rising or falling edge strobe)
●■ Backward compatible configuration select with FPD-Link
●■ Optional second LVDS clock for backward compatibility w/ FPD-Link
●■ Support for two additional user-defined control signals in DC Balanced mode
●■ Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
