The MAX 3000A series high-performance Complex Programmable Logic Device (CPLD) based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 3000A devices operate with a 3.3V supply voltage and provide 600 to 10000 usable gates, ISP, pin-to-pin delays as fast as 4.5ns and counter speeds of up to 227.3MHz. MAX 3000A devices in the -4, -5, -6, -7 and -10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI) and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs and 22V10s to MACH and pLSI devices.
● CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX® architecture
● Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
● Enhanced ISP features
● 4.5ns Pin-to-pin logic delays with counter frequencies of up to 227.3MHz
● Hot-socketing support
● Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
● Industrial temperature range
● PCI Compatible
● Bus-friendly architecture including programmable slew-rate control
● Open-drain output option
● Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls
● Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
● Programmable security bit for protection of proprietary designs
