| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 100 MHz |
| Number of Pins | 44 Pin |
| Supply Voltage (DC) | 3.30 V |
| Case/Package | TQFP-44 |
| Number of Positions | 44 Position |
| Number of Gates | 1250 Gate |
| Number of I/O Pins | 34 IO |
| Number of Inputs and Outputs | 34 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 3.3 V |
| Supply Voltage (Max) | 3.6 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Last Time Buy |
| Packaging | Tray |
| Size-Length | 10 mm |
| Size-Width | 10 mm |
| Size-Height | 0.95 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The EPM3064ATC44-10N is an EEPROM Complex Programmable Logic Device with 1250 usable gates and 64 macro cells. MAX 3000A CPLD is a high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on a MAX® architecture. Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance. The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density small-scale integration (SSI), medium-scale integration (MSI) and large-scale integration (LSI) logic functions.
● Enhanced ISP algorithm for faster programming
● Hot-socketing support
● PCI compatible
● Bus-friendly architecture including programmable slew-rate control
● Open-drain output option
● Programmable power-saving mode for a power reduction of over 50% in each macro cell
● Programmable security bit for protection of proprietary designs
Altera
6 Pages / 0.09 MByte
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47 Pages / 0.41 MByte
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CPLD MAX 3000A Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44Pin TQFP
Altera
CPLD MAX 3000A Family 1.25K Gates 64 Macro Cells 100MHz CMOS Technology 3.3V 44Pin TQFP
Altera
ALTERA EPM3064ATC4410N CPLD, MAX 3000A Series, EEPROM, 64, 34 I/O"s, TQFP, 44Pins, 100MHz
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