| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 166.7 MHz |
| Number of Pins | 44 Pin |
| Supply Voltage (DC) | 5.00 V |
| Case/Package | PLCC-44 |
| Number of Positions | 44 Position |
| Number of Gates | 1250 Gate |
| Number of I/O Pins | 36 IO |
| Number of Inputs and Outputs | 68 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 5 V |
| Supply Voltage (Max) | 5.25 V |
| Supply Voltage (Min) | 4.75 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Not Recommended |
| Packaging | Tube |
| Size-Height | 3.81 mm |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
The EPM7064SLC44-7N is an EEPROM Complex Programmable Logic Device with 1250 usable gates and 64 macro cells. MAX 3000A CPLD is a high-density, high-performance and fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Programmable macro cell flip-flops with individual clear, preset, clock and clock enable controls. The programmable power-saving mode for a reduction of over 50% in each macro cell.
● PCI-compliant device
● Open-drain output
● Programmable security bit for protection of proprietary designs
Altera
67 Pages / 0.46 MByte
Altera
26 Pages / 0.28 MByte
Altera
67 Pages / 0.47 MByte
Altera
18 Pages / 0.47 MByte
Altera
CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 125MHz CMOS Technology 5V 44Pin PLCC
Intel
IC CPLD 64MC 7.5NS 44PLCC
Altera
CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 166.7MHz CMOS Technology 5V 44Pin PLCC
Intel
IC CPLD 64MC 7.5NS 44PLCC
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.
