EPM7064STC44-10N Datasheet PDF - Altera

The EPM7064STC44-10N is a high-density, high-performance Programmable Logic Device (PLD) based on second-generation MAX® architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys and VeriBest.

● Built-in JTAG boundary-scan test

● PCI-compliant devices available

● 5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies

● Open-drain output option

● Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls

● Programmable power-saving mode for a reduction of over 50% in each macrocell

● Six pin or logic-driven output enable signals

● Two global clock signals with optional inversion

● Enhanced interconnect resources for improved routability

● Programmable output slew-rate control