| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 125 MHz |
| Number of Pins | 84 Pin |
| Supply Voltage (DC) | 4.75V (min) |
| Case/Package | PLCC-84 |
| Number of Positions | 84 Position |
| Number of Gates | 2500 Gate |
| Number of I/O Pins | 68 IO |
| Number of Inputs and Outputs | 100 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 5 V |
| Supply Voltage (Max) | 5.25 V |
| Supply Voltage (Min) | 4.75 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Not Recommended |
| Packaging | Tray |
| Size-Height | 3.81 mm |
| Operating Temperature | -40℃ ~ 85℃ (TA) |
The EPM7128SLI84-10N is an EEPROM Complex Programmable Logic Device with 2500 usable gates and 128 macro cells. MAX 3000A CPLD is a high-density, high-performance and fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Programmable macro cell flip-flops with individual clear, preset, clock and clock enable controls. The programmable power-saving mode for a reduction of over 50% in each macro cell.
● PCI-compliant device
● Open-drain output
● Programmable security bit for protection of proprietary designs
Altera
66 Pages / 0.46 MByte
Altera
67 Pages / 0.47 MByte
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66 Pages / 0.41 MByte
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CPLD MAX 7000S Family 2.5K Gates 128 Macro Cells 100MHz CMOS Technology 5V 84Pin PLCC
Intel
IC CPLD 128MC 10NS 84PLCC
Altera
CPLD MAX 7000S Family 2.5K Gates 128 Macro Cells 100MHz CMOS Technology 5V 84Pin PLCC
Intel
IC CPLD 128MC 10NS 84PLCC
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