| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 3 Pin |
| Case/Package | SOT-23-3 |
| Number of Positions | 3 Position |
| Drain to Source Resistance (on) (Rds) | 7.9 Ω |
| Power Dissipation | 350 mW |
| Threshold Voltage | 1 V |
| Input Capacitance | 11 pF |
| Drain to Source Voltage (Vds) | 25 V |
| Rise Time | 8 ns |
| Input Capacitance (Ciss) | 11pF @10V(Vds) |
| Input Power (Max) | 350 mW |
| Fall Time | 5 ns |
| Operating Temperature (Max) | 150 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Power Dissipation (Max) | 350 mW |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2.92 mm |
| Size-Width | 1.3 mm |
| Size-Height | 0.93 mm |
| Operating Temperature | -55℃ ~ 150℃ |
The FDV302P is a P-channel logic level enhancement-mode Digital FET produced using Fairchild"s proprietary high cell density DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. It is designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.
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