FIN3386MTD Datasheet PDF - Fairchild

Description

●The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL (LVTTL) data into four serial Low Voltage Differential Signaling (LVDS) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28-bits of input LVTTL data are sampled and transmitted.

●The FIN3386 receives and converts the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data, acting as the deserializer.

●Features

●Operation -40°C to +85°C

●Low Power Consumption

●20MHz to 85MHz Shift Clock Support

●±1V Common-Mode Range around 1.2V

●Narrow Bus Reduces Cable Size and Cost

●High Throughput (up to 2.38Gbps)

●Internal PLL with No External Component

●Compatible with TIA/EIA-644 Specification

●56-Lead, TSSOP Package