| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 40 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | SOIC |
| Output Current | 2.4 mA |
| Number of Positions | 14 Position |
| Number of Gates | 2 Gate |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage (Max) | 15.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Each |
The HEF4013BT is a Dual D-type Flip-flop features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active high asynchronous CD and SD inputs are independent and override the D or CP inputs. The outputs are buffered for best system performance. The clock input"s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
● Tolerant of slow clock rise and fall times
● Fully static operation
● Standardized symmetrical output characteristics
● Complies with JEDEC standard JESD 13-B
NXP
NXP HEF4013BT Flip-Flop, Complementary, Positive Edge, HEF4013, D, 30ns, 40MHz, 2.4mA, SOIC
NXP
NXP HEF4013BT,653 Flip-Flop, Complementary Output, Positive Edge, HEF4013, D, 30ns, 40MHz, 2.4mA, SOIC
NXP
NXP HEF4013BT,652 Flip-Flop, Complementary, Differential, Positive Edge, HEF4013, D, 30ns, 40MHz, 2.4mA, SOIC
Nexperia
IC D-TYPE POS TRG DUAL 14SOIC
Nexperia
IC D-TYPE POS TRG DUAL 14SOIC
NXP
NXP HEF4013BP Flip-Flop, HEF4013, D, 30ns, 40MHz, 2.4mA, DIP
NXP
Flip Flop D-Type Pos-Edge 2Element 14Pin TSSOP T/R
Nexperia
IC D-TYPE POS TRG DUAL 14TSSOP
Nexperia
IC D-TYPE POS TRG DUAL 14SOIC
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