| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 30 MHz |
| Number of Pins | 16 Pin |
| Capacitance | 7.5 pF |
| Case/Package | SOIC-16 |
| Number of Outputs | 1 Output |
| Output Current | 2.4 mA |
| Supply Current | 16 µA |
| Number of Positions | 16 Position |
| Clock Speed | 30 MHz |
| Number of Bits | 2 Bit |
| Power Dissipation | 500 mW |
| Input Capacitance | 7.5 pF |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 3V ~ 15V |
| Supply Voltage (Max) | 15.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Operating Temperature | -40℃ ~ 85℃ |
The HEF4027BT is a dual JK Flip-flop features independent set-direct (SD), clear-direct (CD), clock inputs and outputs (Q, Q\\). Data is accepted when clock is low and transferred to the output on the positive-going edge of the clock. The active high asynchronous clear-direct and set-direct inputs are independent and override the J, K and clock inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
● Fully static operation
● Standardized symmetrical output characteristics
● Complies with JEDEC standard JESD 13-B
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