| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | SOIC |
| Number of Positions | 16 Position |
| Clock Speed | 35 MHz |
| Number of Gates | 1 Gate |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage (Max) | 15.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Each |
| Size-Length | 10 mm |
| Size-Width | 4 mm |
| Size-Height | 1.45 mm |
The HEF4521BT is a 24-stage Frequency Divider and Oscillator consists of an overriding asynchronous master reset input (MR) and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) functions as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in low-power mode when pins VSS1 and VDD1 are supplied via external resistors. Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B counts up to 224 = 16777216. The counting advances on the high-to-low transition of the clock (A2). The outputs from each of the last seven stages (218 to 224) are available for additional flexibility. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.
● Low power crystal oscillator operation
● Fully static operation
● Standardized symmetrical output characteristics
● Complies with JEDEC standard JESD 13-B
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