LCMXO640C-3TN100C Datasheet PDF - Lattice Semiconductor

The MachXO series Complex Programmable Logic Device (CPLD) with low capacity FPGAs, features glue logic, bus bridging, bus interfacing, power-up control and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-ON capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO.

● Non-volatile, infinitely reconfigurable

● Sleep mode

● TransFR™ reconfiguration (TFR)

● High I/O to logic density

● Embedded and distributed memory

● Flexible I/O buffer

● sysCLOCK™ PLLs

● System level support