Part Datasheet Search > TI > LM3S6965-EQC50-A1 Datasheet PDF
LM3S6965-EQC50-A1 Datasheet PDF - TI
Manufacturer: | TI |
Description: | Stellaris® LM3S6965 Microcontroller |
Documentation: | LM3S6965-EQC50-A1 Datasheet (761 Pages)Pinout Diagram on160 Page172 Page336 Page396 Page433 PageHot Package Outline Dimension on52 Page749 Page750 Page752 Page753 Page Part Numbering System on747 Page |
Pictures: |
LM3S6965-EQC50-A1 Datasheet PDF
ADatasheet has not yet included the datasheet for LM3S6965-EQC50-A1
If necessary, please send a supplementary document request to the administrator
LM3S6965-EQC50-A1 Datasheet PDF (761 Pages)
View Datasheet
Click page to view the detail
LM3S6965-EQC50-A1 Function Overview
Architectural Overview
●The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.
●The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity
●capabilities. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC and PHY available in an ARM architecture MCU.
●Product Features
●The LM3S6965 microcontroller includes the following product features:
●■ 32-Bit RISC Performance
●– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
●applications
●– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
●counter with a flexible control mechanism
●– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
●– 50-MHz operation
●– Hardware-division and single-cycle-multiplication
●– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
●handling
●– 38 interrupts with eight priority levels
●– Memory protection unit (MPU), providing a privileged mode for protected operating system
●functionality
●– Unaligned data access, enabling data to be efficiently packed into memory
●– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
●peripheral control
●■ ARM® Cortex™-M3 Processor Core
●– Compact core.
●– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
●memory size usually associated with 8- and 16-bit devices; typically in the range of a few
●kilobytes of memory for microcontroller class applications.
●– Rapid application execution through Harvard architecture characterized by separate buses
●for instruction and data.
●– Exceptional interrupt handling, by implementing the register manipulations required for handling
●an interrupt in hardware.
●– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
●– Memory protection unit (MPU) to provide a privileged mode of operation for complex
●applications.
●– Migration from the ARM7™ processor family for better performance and power efficiency.
●– Full-featured debug solution
●• Serial Wire JTAG Debug Port (SWJ-DP)
●• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
●• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
●and system profiling
●• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
●• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
●– Optimized for single-cycle flash usage
●– Three sleep modes with clock gating for low power
●– Single-cycle multiply instruction and hardware divide
●– Atomic operations
●– ARM Thumb2 mixed 16-/32-bit instruction set
●– 1.25 DMIPS/MHz
●■ JTAG
●– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
●– Four-bit Instruction Register (IR) chain for storing JTAG instructions
●– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
●– ARM additional instructions: APACC, DPACC and ABORT
●– Integrated ARM Serial Wire Debug (SWD)
●■ Hibernation
●– System power control using discrete external regulator
●– Dedicated pin for waking from an external signal
●– Low-battery detection, signaling, and interrupt generation
●– 32-bit real-time clock (RTC)
●– Two 32-bit RTC match registers for timed wake-up and interrupt generation
●– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
●– RTC predivider trim for making fine adjustments to the clock rate
●– 64 32-bit words of non-volatile memory
●– Programmable interrupts for RTC match, external wake, and low battery events
●■ Internal Memory
●– 256 KB single-cycle flash
●• User-managed flash block protection on a 2-KB block basis
●• User-managed flash data programming
●• User-defined and managed flash-protection block
●– 64 KB single-cycle SRAM
●■ GPIOs
●– 0-42 GPIOs, depending on configuration
●– 5-V-tolerant in input configuration
●– Fast toggle capable of a change every two clock cycles
●– Programmable control for GPIO interrupts
●• Interrupt generation masking
●• Edge-triggered on rising, falling, or both
●• Level-sensitive on High or Low values
●– Bit masking in both read and write operations through address lines
●– Can initiate an ADC sample sequence
●– Pins configured as digital inputs are Schmitt-triggered.
●– Programmable control for GPIO pad configuration
●• Weak pull-up or pull-down resistors
●• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
●configured with an 18-mA pad drive for high-current applications
●• Slew rate control for the 8-mA drive
●• Open drain enables
●• Digital input enables
●■ General-Purpose Timers
●– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
●timers/counters. Each GPTM can be configured to operate independently:
●• As a single 32-bit timer
●• As one 32-bit Real-Time Clock (RTC) to event capture
●• For Pulse Width Modulation (PWM)
●• To trigger analog-to-digital conversions
●– 32-bit Timer modes
●• Programmable one-shot timer
●• Programmable periodic timer
●• Real-Time Clock when using an external 32.768-KHz clock as the input
●• User-enabled stalling when the controller asserts CPU Halt flag during debug
●• ADC event trigger
●– 16-bit Timer modes
●• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
●• Programmable one-shot timer
●• Programmable periodic timer
●• User-enabled stalling when the controller asserts CPU Halt flag during debug
●• ADC event trigger
●– 16-bit Input Capture modes
●• Input edge count capture
●• Input edge time capture
●– 16-bit PWM mode
●• Simple PWM mode with software-programmable output inversion of the PWM signal
show more
LM3S6965-EQC50-A1 Documents
LM3S6965EQC50 Documents
TI
MCU 32Bit Stellaris ARM Cortex M3 RISC 256KB Flash 2.5V/3V/3.3V 100Pin LQFP
TI
MCU 32Bit Stellaris ARM Cortex M3 RISC 256KB Flash 2.5V/3V/3.3V 100Pin LQFP T/R
Part Datasheet PDF Search
Example: STM32F103
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.