| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 3 Pin |
| Supply Voltage (DC) | 10.0V (max) |
| Current Rating | 15.0 A |
| Capacitance Tolerance | ±0.1 % |
| Case/Package | SOT-23-3 |
| Output Voltage | 5 V |
| Output Current | 15 mA |
| Supply Current | 60.0 mA |
| Number of Channels | 1 Channel |
| Number of Positions | 3 Position |
| Output Voltage (Max) | 5 V |
| Output Voltage (Min) | 5 V |
| Output Current (Max) | 15 mA |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Accuracy | 8 mV |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2.92 mm |
| Size-Width | 1.3 mm |
| Size-Height | 0.93 mm |
| Operating Temperature | -40℃ ~ 85℃ |
| Temperature Coefficient | ±100 ppm/℃ |
The LM4040AIM3-5.0/NOPB is a Precision Micropower Shunt Voltage Reference, ideal for space critical applications. Advanced design eliminates the need for an external stabilizing capacitor while ensuring stability with any capacitive load, thus making the LM4040-N easy to use. Further reducing design effort is the availability of several fixed reverse breakdown voltages 2.048, 2.500, 3.000, 4.096, 5.000, 8.192 and 10.000V. The minimum operating current increases from 60µA for the 2.5V LM4040-N to 100µA for the 10.0V LM4040-N. All versions have a maximum operating current of 15mA. The LM4040-N utilizes fuse and zener-zap reverse breakdown voltage trim during wafer sort to ensure that the prime parts have an accuracy of better than ±0.1% (A grade) at 25°C. Bandgap reference temperature drift curvature correction and low dynamic impedance ensure stable reverse breakdown voltage accuracy over a wide range of operating temperatures and currents.
● AEC Q-100 grades 1 and 3 available
● No output capacitor required
● Tolerates capacitive loads
● Green product and no Sb/Br
●Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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