The LMK03318 is an ultra-low-noise PLLatinumTM clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution/fanout, and pin-selectable configuration states stored in on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices. The ultra-low jitter reduces bit-error rate (BER) in high-speed serial links.
● Ultra-Low Noise, High Performance
● Jitter: 100-fs RMS Typical, FOUT > 100 MHz
● PSNR: –80 dBc, Robust Supply Noise Immunity
● Flexible Device Options
● Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination
● Pin Mode, I2C Mode, EEPROM Mode
● 71-Pin Selectable Pre-programmed Default Start-Up Options
● Dual Inputs With Automatic or Manual Selection
● Crystal Input: 10 to 52 MHz
● External Input: 1 to 300 MHz
● Frequency Margining Options
● Fine Frequency Margining Using Low-Cost Pullable Crystal Reference
● Glitchless Coarse Frequency Margining (%) Using Output Dividers
● Other Features
● Supply: 3.3-V Core, 1.8-V, 2.5-V, or 3.3-V Output Supply
● Industrial Temperature Range (–40ºC to 85ºC)
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