| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 5 Pin |
| Supply Voltage (DC) | 5.00 V |
| Case/Package | SOT-23-5 |
| Output Current | 40mA @5V |
| Supply Current | 790 µA |
| Number of Circuits | 1 Circuit |
| Number of Channels | 1 Channel |
| Number of Positions | 5 Position |
| Common Mode Rejection Ratio | 88dB ~ 130dB |
| Input Offset Drift | 1.00 µV/K |
| Bandwidth | 2.5 MHz |
| Slew Rate | 1.00 V/μs |
| Gain Bandwidth Product | 2.5 MHz |
| Input Offset Voltage | 37 µV |
| Input Bias Current | 0.2 pA |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Gain Bandwidth | 2.5 MHz |
| Minimum CMRR Range | 88 dB |
| Supply Voltage | 2.7V ~ 12V |
| Supply Voltage (Max) | 12 V |
| Supply Voltage (Min) | 2.7 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2.92 mm |
| Size-Width | 1.6 mm |
| Size-Height | 1.02 mm |
| Operating Temperature | -40℃ ~ 125℃ |
The LMP7701MF is a RRIO Precision Amplifier with a CMOS input stage and a wide supply voltage range. The specified low offset voltage of less than ±200µV along with the specified low input bias current of less than ±1pA make the LMP7701 ideal for precision applications. The amplifier is built utilizing VIP50 technology, which allows the combination of a CMOS input stage and a 12V common mode and supply voltage range. This makes the amplifier is great choices in many applications where conventional CMOS parts cannot operate under the desired voltage conditions. The amplifier has a rail-to-rail input stage that significantly reduces the CMRR glitch commonly associated with it. This is achieved by trimming both sides of the complimentary input stage, thereby reducing the difference between the NMOS and PMOS offsets. The output of the amplifier swings within 40mV of either rail to maximize the signal dynamic range in applications requiring low supply voltage.
● 715µA Supply current
● Rail-to-rail input and output
● 130dB CMRR
● 9nV/√Hz Input voltage noise
● ±200fA Input bias current
● ±200µV Maximum Input offset voltage
●This device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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