| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 1.4 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00V (min) |
| Case/Package | SOIC-16 |
| Halogen Free Status | Halogen Free |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Duty Cycle | 50 % |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 10.45 mm |
| Size-Width | 7.6 mm |
| Size-Height | 2.4 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The MC14046BDWR2G is a Phase Locked Loop contains two phase comparators, a voltage-controlled oscillator (VCO), source follower and zener diode. The comparators have two common signal inputs, PCAin and PCBin. Input PCAin can be used directly coupled to large voltage signals or indirectly coupled (with a series capacitor) to small voltage signals. The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1out and maintains 90 phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals, PC2out and LD and maintains a 0 phase shift between PCAin and PCBin signals (duty cycle is immaterial). The linear VCO produces an output signal VCOout whose frequency is determined by the voltage of input VCOin and the capacitor and resistors connected to pins C1A, C1B, R1 and R2.
● Buffered outputs compatible with HTL and low-power TTL
● Diode protection on all inputs
ON Semiconductor
8 Pages / 0.12 MByte
ON Semiconductor
9 Pages / 0.12 MByte
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2 Pages / 0.05 MByte
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Phase Locked Loops - PLL LOG CMOS PLL
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Phase Locked Loop, CMOS, PDSO16, SOIC-16
ON Semiconductor
PLL, 1.4MHz, 3V to 18V, SOIC-16
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