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MCIMX6U5DVM10AC Datasheet PDF - NXP
Manufacturer: | NXP |
Category: | Microprocessors |
Case Package: | BGA-624 |
Description: | MPU i.MX 6 RISC 32Bit 1000MHz 1.8V/2.5V/2.8V/3.15V 624Pin MAPBGA Tray |
Documentation: | MCIMX6U5DVM10AC Datasheet (2 Pages)MCIMX6U5DVM10AC User Reference Manual Guide (5783 Pages)MCIMX6U5DVM10AC Programming Manual (22 Pages)MCIMX6U5DVM10AC Application Note (170 Pages) |
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MCIMX6U5DVM10AC Datasheet PDF
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MCIMX6U5DVM10AC Datasheet PDF (2 Pages)
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MCIMX6U5DVM10AC Specifications
TYPE | DESCRIPTION |
---|---|
Mounting Style | Surface Mount |
Number of Pins | 624 Pin |
Supply Voltage (DC) | 1.35V (min) |
Case/Package | BGA-624 |
Number of Positions | 624 Position |
Clock Speed | 1.00 GHz |
RAM Memory Size | 128 KB |
Operating Temperature (Max) | 95 ℃ |
Operating Temperature (Min) | 0 ℃ |
Supply Voltage (Max) | 1.5 V |
Supply Voltage (Min) | 1.35 V |
MCIMX6U5DVM10AC Size & Package
TYPE | DESCRIPTION |
---|---|
Product Lifecycle Status | Active |
Packaging | Tray |
Operating Temperature | 0℃ ~ 95℃ |
MCIMX6U5DVM10AC Environmental
MCIMX6U5DVM10AC Export Classifications
MCIMX6U5DVM10AC Function Overview
● The i.MX 6Solo supports single ARM Cortex-A9 MPCore (with TrustZone)
● The i.MX 6DualLite supports dual ARM Cortex-A9 MPCore (with TrustZone)
● The core configuration is symmetric, where each core includes:
● 32 KByte L1 Instruction Cache
● 32 KByte L1 Data Cache
● Private Timer and Watchdog
● Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The ARM Cortex-A9 MPCore™ complex includes:
● General Interrupt Controller (GIC) with 128 interrupt support
● Global Timer
● Snoop Control Unit (SCU)
● 512 KB unified I/D L2 cache:
● Used by one core in i.MX 6Solo
● Shared by two cores in i.MX 6DualLite
● Two Master AXI bus interfaces output of L2 cache
● Frequency of the core (including NEON and L1 cache).
● NEON MPE coprocessor
● SIMD Media Processing Architecture
● NEON register file with 32x64-bit general-purpose registers
● NEON Integer execute pipeline (ALU, Shift, MAC)
● NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
● NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components:
● Boot ROM, including HAB (96 KB)
● Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
● Secure/non-secure RAM (16 KB)
● External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards.
● 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and LV-DDR3-800 in i.MX 6Solo; 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and LV-DDR3-800, supporting DDR interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite
● 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
● 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.
● 16/32-bit PSRAM, Cellular RAM Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):
● Displays-Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC).
● One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz)
● LVDS serial ports-One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example, WUXGA at 60 Hz) each
● HDMI 1.4 port
● MIPI/DSI, two lanes at 1 Gbps
● EPDC, Color, and monochrome E-INK, up to 1650x2332 resolution and 5-bit grayscale
● Camera sensors:
● Two parallel Camera ports (up to 20 bit and up to 240 MHz peak)
● MIPI CSI-2 Serial port, supporting from 80 Mbps to 1 Gbps speed per data lane. The CSI-2 Receiver core can manage one clock lane and up to two data lanes. Each i.MX 6Solo/6DualLite processor has two lanes.
● Expansion cards:
● Four MMC/SD/SDIO card ports all supporting:
● 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max)
● 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)
● USB:
● One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
● Three USB 2.0 (480 Mbps) hosts:
● One HS host with integrated High Speed Phy
● Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy
● Expansion PCI Express port (PCIe) v2.0 one lane
● PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration.
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