MSC8156ADS Datasheet PDF - NXP

The MSC8156 application development system is a complete debugging environment intended for engineers developing applications for the MSC8156 family of NXP digital signal processors (DSPs) targeting high-bandwidth highly computational DSP applications. It is optimized for 3GPP, TD-SCDMA, 3G-LTE, and WiMAX applications. The MSC8156 contains six StarCore SC3850 DSP subsystems (48 GMACS at 1 GHz).

● 1 MB of M3 shared memory

● Two DDR2/DDR3 memory controllers with a 64-bit data rate up to 800 M

● High speed serial interface (HSSI) with two 4-channel SerDes ports

● Dual RISC QUICC Engine™ subsystem

● Two Dallas E1/T1 framers connect to the four DSP TDM ports

● P1 and P3 connectors carry the DSP GPIO and TDM signals

● A DIP switch array and associated FPGA supports the DSP configuration and boot support at reset