| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 210 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.97V (min) |
| Case/Package | TSSOP-16 |
| Halogen Free Status | Halogen Free |
| Number of Outputs | 2 Output |
| Output Current | 25 mA |
| Supply Current | 75 mA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Duty Cycle | 50 % |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | 40 ℃ |
| Supply Voltage | 2.97V ~ 3.63V |
| Supply Voltage (Max) | 3.63 V |
| Supply Voltage (Min) | 2.97 V |
| Input Voltage | 3.3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 5.1 mm |
| Size-Width | 4.5 mm |
| Size-Height | 1.05 mm |
| Weight | 0.0027678208248 kg |
| Operating Temperature | -40℃ ~ 85℃ |
The NB3N3020DTG is a low-phase noise selectable Clock Multiplier takes a 5 to 27MHz fundamental mode parallel resonant crystal or a 2 to 210MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri-level (low, mid, high) LVCMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. The LVCMOS/LVTTL output enable (OE1) tri-states the LVCMOS/LVTTL clock output (CLK1) when low. When the LVTTL/LVCMOS output enable (OE2) is LOW, LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
● External loop filter is not required
● LVPECL Differential output
● LVCMOS/LVTTL outputs
● RMS period jitter of 5ps
ON Semiconductor
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3.3V LVPECL/ LVCMOS Programmable Clock Multiplier
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Clock Generator 2MHz to 210MHz Input 210MHz Output 16Pin TSSOP Rail
ON Semiconductor
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ON Semiconductor
Board Eval Nb3n3020 Clock Mult
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