| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 3 Pin |
| Case/Package | TO-220-3 |
| Number of Positions | 3 Position |
| Drain to Source Resistance (on) (Rds) | 0.041 Ω |
| Power Dissipation | 60 W |
| Threshold Voltage | 700 mV |
| Drain to Source Voltage (Vds) | 20 V |
| Rise Time | 27 ns |
| Input Capacitance (Ciss) | 1590pF @10V(Vds) |
| Input Power (Max) | 60 W |
| Fall Time | 70 ns |
| Operating Temperature (Max) | 175 ℃ |
| Operating Temperature (Min) | -65 ℃ |
| Power Dissipation (Max) | 60 W |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Rail, Tube |
| Size-Length | 10.67 mm |
| Size-Width | 4.7 mm |
| Size-Height | 16.3 mm |
| Operating Temperature | -65℃ ~ 175℃ |
The NDP6020P is a P-channel logic level enhancement mode Field Effect Transistor using high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC/DC converters, PWM motor controls and other battery powered circuits where fast switching, low in-line power loss and resistance to transients are needed.
● Critical DC electrical parameters specified at elevated temperature
● Internal source drain diode can eliminate need for an external Zener diode transient suppressor
● High density cell design for extremely low RDS (ON)
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