PCA9512ADP Datasheet PDF - NXP

The PCA9512ADP is a level shifting hot swappable I²C-bus and SMBus bus Buffer allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 and 5V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 to 5.5V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop-bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the buffer provides bi-directional buffering, keeping the backplane and card capacitances isolated.

● Supports clock stretching and multiple master arbitration and synchronization

● ESD protection exceeds 2000V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101

● Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA

●ESD sensitive device, take proper precaution while handling the device.