The PCA9517DP,118 is a level translating CMOS I²C-Bus Repeater provides level shifting between low voltage and higher voltage I²C-bus or SMBus applications. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bi-directional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400pF. Using the repeater enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the repeater is unpowered. The 2.7 to 5.5V bus port-B drivers behave much like the drivers on this device, while the adjustable voltage bus port-A drivers drive more current and eliminate the static offset voltage. This results in a low on the port-B translating into a nearly 0V low on the port-A which accommodates smaller voltage swings of lower voltage logic.
● Bidirectional buffer isolates capacitance and allows 400pF on either side of the device
● Footprint and functional replacement
● Active high individual repeater enable input
● Open-drain input/outputs
● Lock-up free operation
● Supports arbitration and clock stretching across the repeater
● Powered-off high-impedance I²C pins
● Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
