SM34020A-S Datasheet PDF - TI

The SM34020A graphics system processor (GSP) is the second generation of an advanced high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed to expedite raster graphics operations, the SM34020A provides user-programmable control of the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The 4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable width data fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.

●The SM34020A is a CMOS 32-bit processor with hardware support for graphics operations such as pixel block transfers (PIXBLTS) during raster operations and curve-drawing algorithms. Also included is a complete set of general-purpose instructions with addressing modes tuned to support high-level languages. In addition to its ability to address a large external memory range, the SM34020A contains 30 general-purpose 32-bit registers, a hardware stack pointer, and a 512-byte instruction cache. On-chip functions include 64 programmable I/O registers that control CRT timing, input/output control, and parameters required by some instructions. The SM34020A directly interfaces to DRAMs and VRAMs and generates raster control signals. The SM34020A can be configured to operate as a standalone processor, or it can be used as a graphics engine with a host system. The host interface provides a generalized communication port for any standard host processor. The SM34020A also accommodates a multiprocessing or direct memory access (DMA) environment through the request/grant interface protocols. Virtual memory systems are supported through bus-fault detection and instruction continuation.

●The SM34020A provides single-cycle execution of general-purpose instructions and most common integer arithmetic and Boolean operations from its instruction cache. Additionally, the SM34020A incorporates a hardware barrel shifter that provides a single-state bidirectional shift-and-rotate function for 1 to 32 bits.

●The local-memory controller is designed to optimize memory access operations. It also supports pipeline memory write operations of variable-sized fields and allows memory access and instruction execution in parallel.

●The SM34020A graphics-processing hardware supports pixel and pixel-array processing capabilities for both monochrome and color systems at a variety of pixel sizes. The hardware incorporates two-operand and three-operand raster operations with Boolean and arithmetic operations, XY addressing, window clipping, window-checking operations, 1 to n bits-per-pixel transforms, transparency, and plane masking. The architecture further supports operations on single pixel transfer (PIXT) instructions or on two-dimensional arrays of arbitrary size (PIXBLTS).

●The SM34020A flexible graphics-processing capabilities allow software-based graphics algorithms without sacrificing performance. These algorithms include clipping to arbitrary window size, custom incremental-curve drawing, two-operand raster operations, and masked two-operand raster operations.

●The SM34020A provides for extensions to the basic architecture through the coprocessor interface. Special instructions and cycle timings are included to enhance data flow to coprocessors without requiring the coprocessor to decode the instruction stream, generate system addresses, or move data for the coprocessor through the SM34020A.

● Class B High-Reliability Processing

● 1-µm CMOS Technology

● Military Operating Temperature Range -40°C to 110°C

● SM34020A-32/40

● 125/100-ns Instruction Cycle Time

● Fully Programmable 32-Bit General-Purpose Processor With 512-Megabyte Linear Address Range (Bit Addressable)

● Second-Generation Graphics System Processor

● Object-Code Compatible With the SMJ34010

● Enhanced Instruction Set

● Optimized Graphics Instructions

● Coprocessor Interface

● Pixel Processing, XY Addressing, and Window Checking Built Into the Instruction Set

● Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit Pixel Size With 16 Boolean and Six Arithmetic Pixel Processing Options (Raster Ops)

● 512-Byte LRU On-Chip Instruction Cache

● Optimized DRAM/VRAM Interface

● Page-Mode for Burst Memory Operations

● Dynamic Bus Sizing (16-Bit and 32-Bit Transfers)

● Byte-Oriented CAS\ Strobes

● Flexible Host Processor Interface

● Supports Host Transfers

● Direct Access to All of the SMJ34020A Address Space

● Implicit Addressing

● Prefetch for Enhanced Read Access

● Programmable CRT Control

● Composite Sync Mode

● Separate Sync Mode

● Synchronization to External Sync

● Direct Support for Special Features of 1M VRAMs

● Load Write Mask

● Load Color Mask

● Block Write

● Write Using the Write Mask

● Flexible Multi-Processor Interface

● Packaging Options

● 145-Pin Grid Array Ceramic Package (GB Suffix)