SMJ320C30 Datasheet PDF - TI

The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted in a less expensive processor that can be designed into systems currently using costly bit-slice processors.

● SMJ320C30-40: 50-ns single-cycle execution time, 5% supply

● SMJ320C30-50: 40-ns single-cycle execution time, 5% supply

●The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/ O, and a short machine-cycle time. High performance and ease of use are results of these features.

●General-purpose applications are enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to dedicated coprocessor.

●High-level language support is implemented easily through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

●For additional information when designing for cold temperature operation, please see Texas Instruments application report _320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature_, literature number SGUA001.

● –55°C to 125°C Operating Temperature Range, QML Processing

● Processed to MIL-PRF-38535 (QML)

● Performance

● SMJ320C30-40 (50-ns Cycle)

●   40 MFLOPS

●   20 MIPS

● SMJ320C30-50 (40-ns Cycle)

●   50 MFLOPS

●   25 MIPS

● Two 1K-Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks

● Validated Ada Compiler

● 64-Word × 32-Bit Instruction Cache

● 32-Bit Instruction and Data Words, 24-Bit Addresses

● 40 / 32-Bit Floating-Point / Integer Multiplier and Arithmetic Logic Unit (ALU)

● Parallel ALU and Multiplier Execution in a Single Cycle

● On-Chip Direct Memory Access (DMA) Controller for Concurrent I/O and CPU Operation

● Integer, Floating-Point, and Logical Operations

● One 4K-Word × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block

● Two 32-Bit External Ports (24- and 13-Bit Address)

● Two Serial Ports With Support for 8- / 16- / 24- / 32-Bit Transfers

● Packaging

● 181-Pin Grid Array Ceramic Package (GB Suffix)

● 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix)

● SMD Approval for 40- and 50-MHz Versions

● Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

● Zero-Overhead Loops With Single-Cycle Branches

● Interlocked Instructions for Multiprocessing Support

● 32-Bit Barrel Shifter

● Eight Extended-Precision Registers (Accumulators)

● Two- and Three-Operand Instructions

● Conditional Calls and Returns

● Block Repeat Capability

● Fabricated Using Enhanced Performance Implanted CMOS (EPIC™) by Texas Instruments

● Two 32-Bit Timers

●EPIC is a trademark of Texas Instruments Incorporated.