The SN65LVDS048APW is a quad differential Line Receiver implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3.3V supply rail. Any of the quad differential receivers will provide a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables.
● Flow-through pin-out simplifies PCB layout
● High impedance LVDS inputs on power-down
● Low-power dissipation (40mW at 3.3V static)
● Accepts small swing (350mV) differential signal levels
● Supports open, short and terminated input failsafe
● Conforms to TIA/EIA-644 LVDS standard
● >400Mbps (200MHz) Signalling rate
● 50ps Typical channel-to-channel skew
● 200ps Typical differential skew
● 2.7ns Typical propagation delay time
● 3.3V Power supply design
● Green product and no Sb/Br
