| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | SOIC-20 |
| Number of Outputs | 8 Output |
| Output Current | 24 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 12.0 ns |
| Polarity | Non-Inverting |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 12.8 mm |
| Size-Width | 7.52 mm |
| Size-Height | 2.35 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74ACT573DW is an octal transparent D Latch with 3-state outputs. It features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The eight latches are D-type transparent latches. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in a bus-organized system without need for interface or pull-up components.
● Inputs are TTL-voltage compatible
● Green product and no Sb/Br
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